Three dimensional (3D) integration promises to reduce system form factor through direct stacking and interconnection of chips, made using different technologies, into a single system. These interconnects consist of small and deep through-wafer vias in the form of metal (e.g., copper) nails. Vias are generally vertical electrical connectors that electrically connect different generally horizontal levels of circuitry, and in the case of the present invention, electrically connect electrical circuits on distinct integrated circuit chips. One of the enabling technologies to achieve 3D stacks, is thinning of the base wafer on which the semiconductor circuits (integrated circuits) are disposed. Semiconductor wafer manufacturing typically involves hundreds of discrete operations on the surface of a silicon wafer, which are performed over a number of weeks. In order to minimize wafer breakage and damage, which can easily occur during this lengthy manufacturing process, the base wafers are typically 300- to 800-microns thick. The base wafer is thinned by removing base wafer material (e.g., silicon in case of silicon wafer processing) from the backside of the wafer. This can involve gluing the front side of a wafer comprising an integrated circuit thereon to a carrier wafer, and then grinding, and then CMP of the backside of the wafer to achieve a thickness of about 10 to 50 microns, while the wafer is temporarily glued to a carrier. This thinning exposes conductive vias extending at least partially through (e.g., completely through) the base wafer.
The grinding step has been considered necessary because CMP processes, especially for silicon, have historically been very limited in rate. However, wafer delamination and destruction, as well as destruction of the grinding wheels, has been an unfortunate, but not uncommon, problem with grinding of the backside of a silicon wafer. This is particularly problematic, because the wafer represents the end-product of a number of elaborate fabrication and quality control steps, and failures of these wafers, therefore, represent significant economic loss. Further, destruction of grinding wheels results in considerable line down time, as well as resulting in additional economic loss.
What is needed is a CMP process capable of polishing base wafer material (e.g., silicon in case of a silicon wafer) at a sufficiently high rate so that the grinding step can be eliminated. Even in processes where back-side material is ground in a grinding step, the use of high removal rate CMP can allow manufacturers to specify less material that needs to be ground from the backside of wafers.
Chemical mechanical planarization (chemical mechanical polishing, CMP) for planarization of semiconductor substrates is now widely known to those skilled in the art and has been described in numerous patents and open literature publications. Some introductory references on CMP are as follows: “Polishing Surfaces for Integrated Circuits”, by B. L. Mueller and J. S. Steckenrider, Chemtech, February, 1998, pages 38-46; H. Landis et al., Thin Solids Films, 220 (1992), page 1; and “Chemical-Mechanical Polish” by G. B. Shinn et al., Chapter 15, pages 415-460, in Handbook of Semiconductor Manufacturing Technology, editors: Y. Nishi and R. Doering, Marcel Dekker, New York City (2000).
In a typical CMP process, a substrate (e.g., a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically an abrasive and chemically reactive mixture, is supplied to the pad during CMP processing of the substrate. During the CMP process, the pad (fixed to the platen) and substrate are rotated, while a wafer carrier system or polishing head applies pressure (downward force) against the substrate. The slurry accomplishes the planarization (polishing) process by chemically and mechanically interacting with the substrate film being planarized, due to the effect of the downward force and the rotational movement of the pad relative to the substrate. Polishing is continued in this manner until the desired film on the substrate is removed, with the usual objective being to effectively planarize the substrate. Typically metal CMP slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium.
Silicon based semiconductor devices, such as integrated circuits (ICs), also known as integrated circuit chips, typically include a dielectric layer, metal line circuits, transistor switches forming memory and computational features, as well as capacitors and additional integrated circuit electrical devices making up a complete, operational electrical processing or memory device. Multilevel circuit traces, typically formed from aluminum or an aluminum alloy or copper, are patterned onto the dielectric layer substrate. There are numerous types of layers that can be polished by CMP, for example, silicon nitride, interlayer dielectrics (ILD) such as silicon oxide and low-k films, including carbon-doped oxides; metal layers, such as tungsten, copper, aluminum, etc., which are used to connect the active devices; barrier layer materials such as titanium, titanium nitride, tantalum, tantalum nitride, noble metals, etc.